In some applications it is necessary to maintain bit alignment after multiplexing or demultiplexing a number of parallel bit streams into a different number of parallel bit streams. For instance, in a coherent fiber optic communication system using quadrature phase-shift keying, differential encoding is used to eliminate phase ambiguities at the receiver. As a result, parallel data output streams which drive the in-phase and quadrature-phase optics must be bit-aligned to maintain the differential encoding.
More specifically, a chain of dividers provide various clock signals to the multiplexor/demultiplexor circuits in order to increase and/or decrease the clocking frequencies throughout the entire circuit. However, the state of each divider generating a local clock at any particular point in time is randomly set, because of the random states of internal circuitry (e.g., flip-flops, etc.) contained within the dividers. In that case, the phase of the data output streams are not aligned. This is especially true in circuits driving in-phase and quadrature-phase optics using parallel data output streams.
One approach to achieve bit alignment is to implement a common clock divider circuit which generates all the required clocks. In a parallel configuration of multiple multiplexors/demultiplexors, the clocks are then distributed to the macros or subunits of the multiplexors/demultiplexors, including clocking units (e.g., dividers), requiring some form of a common clock. Yet another approach is to locally generate the multiple clocks within each macro describing repeated circuit blocks. Thereafter, the phase of the divider outputs generated by each of the macros is then inverted as required to achieve phase matching.
However, in both of the above approaches used to achieve bit alignment, the circuits require increased power to drive multiple long clock networks to ensure the highest quality of the distributed clocks. In addition, there is increased difficulty in designing the routing throughout the multiple clock networks, as separate routing of a clock from a common source to each divider is required. Also, the previous methodologies experience difficulty in scaling to larger number of parallel outputs when performing bit alignment.
Additionally, automated testing of a clocking circuit in a multiplexor/demultiplexor is desired. However, because the clocking circuits of traditional multiplexor/demultiplexor circuits start up in a random state, circuit outputs cannot be easily compared against expected outputs, which makes automated testing difficult.